Job Title:  Principal Pixel Architect


Pasadena, CA, US, 91107

Business Unit:  Vision Research
Posting Date:  Nov 10, 2023
Job Description: 

Forza Silicon is a Business Unit in the Materials Analysis Division of AMETEK, Inc. Forza’s history begins at the formation of the CMOS imaging industry where company co-founders, Barmak Mansoorian and Daniel Van Blerkom were a critical part of the Photobit team. Along with Photobit Co-founder, Dr. Eric Fossum, and many others, the team pioneered the development of CMOS imaging technology. Founded in 2001, Forza Silicon has established itself as an innovator and industry leader in the field of mixed-signal IC and CMOS imaging designs that have set the standard of the possible. Primarily through long standing customer relationships and partner referrals, Forza has grown to where today the company employs one of the industry’s largest and most experienced independent CMOS imaging engineering teams.  To learn more about Forza Silicon, please go to


Position Summary:

This position will report to the engineering director and assume responsibility to design, layout and optimize pixels for custom CMOS image sensors. The candidate will be expected to lead pixel IP development and work closely with analog and digital designers in defining pixel and readout timing requirements and optimize noise performance. The candidate will also be expected to interface extensively with foundry partners to understand process details in support of design implementation and external vendors to communicate specifications, design status, technical details, etc.


The candidate will also be expected to contribute to overall sensor architecture and design, including specification and design of pixel readout path, reference and power supply generation and distribution, and pixel control logic.  Ideally the candidate will be able to coordinate top chip integration of pixel design, readout path, and support circuitry into a design ready for tapeout.


Primary Responsibilities:

  • Design, layout, and optimization of CIS pixels for different types of pixel architectures and applications. Examples include global shutter, rolling shutter, CTIA, dual gain, LOFIC etc.
  • Lead pixel IP development by architecting test chips consisting of several pixel design of experiment (DOE).
  • Interface with foundry partners to understand process details in support of design implementation, manage pixel design and performance, and oversee tapeout and fabrication.
  • Perform TCAD simulations to estimate pixel performance and understand tradeoffs whenever required in a project. This is particularly critical when a reference pixel IP is not provided by the foundry.
  • Work with customers to understand pixel requirements, translate requirements to detailed specification, and develop pixel architecture to ensure specifications are met.
  • Develop and implement sensor architectures to leverage pixel and process capabilities to meet challenging design specifications.
  • Lead analog and digital CIS designers in architecture and implementation of readout and other support circuitry to meet challenging requirements -- optimizing noise performance, pixel settling etc.
  • Work with test engineers to facilitate development of test hardware, test plans, and oversee overall sensor and pixel bring-up and characterization efforts and results.


Position Requirements:

  • M.S. in Electrical Engineering, Physics or Applied Physics (Ph.D. preferred)
  • A strong background in solid state device physics is preferred.
  • Broad understanding of optics/optoelectronics is a huge plus.
  • 7+ years of experience in design of image sensors is required.
  • A deep understanding of different pixel architectures and operation.
  • Understanding of semiconductor fab processing and process integration, and how these steps affect electrical and optical performance of CIS pixels.
  • Knowledge of TCAD (Sentaurus or similar software) process simulation tools is a must.
  • Detailed understanding of CIS readout architecture and a background in mixed signal design with experience designing analog blocks like single-slope ADC, PLL, LDO etc. is a huge plus.
  • Work closely with Design, Product Engineering, Probe, and Characterization engineering teams to optimize pixel design
  • Ability to multitask and manage priorities for different CIS projects in various process nodes.
  • Good verbal and written communication skills for effective communication to multiple teams across various time zones


Salary Minimum:  $200,000
Salary Maximum:  $200,000 +
Incentive:  Yes

Disclaimer: Where a specific pay range is noted, it is a good faith estimate at the time of this posting.  The actual salary offered will be based on experience, skills, qualifications, market / business considerations, and geographic location.

AMETEK is committed to making a safer, sustainable, and more productive world a reality. We use differentiated technology solutions to solve our customers’ most complex challenges. We employ 18,500 colleagues, in 30 countries, that are grounded by our core values: Ethics and Integrity, Respect for the Individual, Diversity and Inclusion, Teamwork, and Social Responsibility. AMETEK is a leading global provider of industrial technology solutions serving a diverse set of attractive niche markets with annual sales of over $6.0 billion. Traded publicly (NYSE:AME), we are a component of the S&P 500. Visit for more information.

We are an Equal Opportunity Employer and do not discriminate against any employee or applicant for employment because of race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, and basis of disability or any other federal, state or local protected class. Individuals who need a reasonable accommodation because of a disability for any part of the employment process should call 1 (866) 263-8359.

Nearest Major Market: Los Angeles